Displaying 10 results from an estimated 10 matches for "ssub_0".
2013 Oct 07
1
[LLVMdev] Subregister liveness tracking
...he 'D0' register but later reading the 'S0' and 'S1' components
separately.
This is modeled with subregister operands which specify that only parts
of a
wider value are accessed. For example the register class of the 'DXX'
registers supports subregisters calls 'ssub_0' and 'ssub_1' which would
result in 'S4' and 'S5' getting used if 'D2' is assigned to the virtual
register later.
Typical operations are decomposing wider values or composing wide values
with
multiple smaller defs:
Decomposing:
%vreg1<def> = produce a ...
2013 Oct 08
2
[LLVMdev] Subregister liveness tracking
...the 'S0' and 'S1' components
> separately.
> This is modeled with subregister operands which specify that only
> parts of a
> wider value are accessed. For example the register class of the 'DXX'
> registers supports subregisters calls 'ssub_0' and 'ssub_1' which
> would
> result in 'S4' and 'S5' getting used if 'D2' is assigned to the
> virtual
> register later.
>
> Typical operations are decomposing wider values or composing wide
> values with
> mul...
2013 Oct 08
0
[LLVMdev] Subregister liveness tracking
...the 'S0' and 'S1' components
>> separately.
>> This is modeled with subregister operands which specify that only parts
>> of a
>> wider value are accessed. For example the register class of the 'DXX'
>> registers supports subregisters calls 'ssub_0' and 'ssub_1' which would
>> result in 'S4' and 'S5' getting used if 'D2' is assigned to the virtual
>> register later.
>>
>> Typical operations are decomposing wider values or composing wide values
>> with
>> multiple smaller...
2013 Oct 09
4
[LLVMdev] Subregister liveness tracking
...but later reading the 'S0' and 'S1' components separately.
>> This is modeled with subregister operands which specify that only parts of a
>> wider value are accessed. For example the register class of the 'DXX'
>> registers supports subregisters calls 'ssub_0' and 'ssub_1' which would
>> result in 'S4' and 'S5' getting used if 'D2' is assigned to the virtual
>> register later.
>>
>> Typical operations are decomposing wider values or composing wide values with
>> multiple smaller defs:
&g...
2010 Jun 15
4
[LLVMdev] Simpler subreg ops in machine code IR
...eg operations with less redundancy:
%reg1045<def> = EXTRACT_SUBREG %reg1044<kill>, 4
%reg1045<def> = COPY %reg1044:sub_32bit<kill>
%reg1045<def> = INSERT_SUBREG %reg1045, %reg1044<kill>, 4
%reg1045:sub_32bit<def> = COPY %reg1044<kill>
%reg1050:ssub_0<def> = EXTRACT_SUBREG %reg1060:dsub_1<kill>, ssub_0
%reg1050:ssub_0<def> = COPY %reg1060:ssub_2<kill>
It will also replace the TargetInstrInfo::copyRegToReg hook when copying virtual registers:
%reg1050 = COPY %reg1044<kill>
It will be lowered with a TII.copyRegTo...
2010 Jun 16
0
[LLVMdev] Simpler subreg ops in machine code IR
...> %reg1045<def> = EXTRACT_SUBREG %reg1044<kill>, 4
> %reg1045<def> = COPY %reg1044:sub_32bit<kill>
>
> %reg1045<def> = INSERT_SUBREG %reg1045, %reg1044<kill>, 4
> %reg1045:sub_32bit<def> = COPY %reg1044<kill>
>
> %reg1050:ssub_0<def> = EXTRACT_SUBREG %reg1060:dsub_1<kill>, ssub_0
> %reg1050:ssub_0<def> = COPY %reg1060:ssub_2<kill>
>
> It will also replace the TargetInstrInfo::copyRegToReg hook when copying virtual registers:
>
> %reg1050 = COPY %reg1044<kill>
>
> It w...
2012 Mar 31
1
[LLVMdev] CompositeIndices
Does anyone know exactly what ComposerIndices in Target.td is all about?
I see just one place where it's used in X86 but it's not clear from the
comments in Target.td and it's one usage, exactly what this feature is
about.
Tia.
Reed
2010 Nov 27
3
[LLVMdev] Register Pairing
...6384, %R23R22 in reg%16385
Function Live Outs: %R25R24
BB#0: derived from LLVM BB %entry
Live Ins: %R25R24 %R23R22
%reg16385<def> = COPY %R23R22; WDREGS:%reg16385 // COPY B
%reg16384<def> = COPY %R25R24; WDREGS:%reg16384 // COPY A
%reg16387<def> = COPY %reg16384:ssub_0; GPR8:%reg16387 WDREGS:%reg16384
// EXTRACT LO BYTE OF A
%reg16388<def> = COPY %reg16385:ssub_0; GPR8:%reg16388 WDREGS:%reg16385
// EXTRACT LO BYTE OF B
%reg16389<def> = COPY %reg16384:ssub_1; GPR8:%reg16389 WDREGS:%reg16384
// EXTRACT HI BYTE OF A
%reg16390<def> = COP...
2013 May 16
1
[LLVMdev] Combining physical registers
...gisters. Both sub_32bit and sub_16bit have
/// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
/// sub_32bit sub-register.
///
/// On the other hand, the ARM NEON lanes fully cover their registers: The
/// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
/// This is related to the CoveredBySubRegs property on register definitions.
///
/// This function returns a bit mask of lanes that completely cover their
/// sub-registers. More precisely, given:
///
/// Covering = getCoveringLanes();
/// MaskA = getSubRegIndex...
2013 May 16
2
[LLVMdev] Combining physical registers
The function TII::canCombineSubRegIndices has been gone for a while now,
and I was wondering if there is a target-independent way of determining
if a certain set of physical registers "adds up" to a larger register.
For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1
are D0.
The context here is an attempt to coalesce multiple loads/stores into
fewer loads/stores