Displaying 7 results from an estimated 7 matches for "reg1050".
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reg1030
2010 Jun 15
4
[LLVMdev] Simpler subreg ops in machine code IR
...les subreg operations with less redundancy:
%reg1045<def> = EXTRACT_SUBREG %reg1044<kill>, 4
%reg1045<def> = COPY %reg1044:sub_32bit<kill>
%reg1045<def> = INSERT_SUBREG %reg1045, %reg1044<kill>, 4
%reg1045:sub_32bit<def> = COPY %reg1044<kill>
%reg1050:ssub_0<def> = EXTRACT_SUBREG %reg1060:dsub_1<kill>, ssub_0
%reg1050:ssub_0<def> = COPY %reg1060:ssub_2<kill>
It will also replace the TargetInstrInfo::copyRegToReg hook when copying virtual registers:
%reg1050 = COPY %reg1044<kill>
It will be lowered with a TII.co...
2010 Jun 16
0
[LLVMdev] Simpler subreg ops in machine code IR
...cy:
>
> %reg1045<def> = EXTRACT_SUBREG %reg1044<kill>, 4
> %reg1045<def> = COPY %reg1044:sub_32bit<kill>
>
> %reg1045<def> = INSERT_SUBREG %reg1045, %reg1044<kill>, 4
> %reg1045:sub_32bit<def> = COPY %reg1044<kill>
>
> %reg1050:ssub_0<def> = EXTRACT_SUBREG %reg1060:dsub_1<kill>, ssub_0
> %reg1050:ssub_0<def> = COPY %reg1060:ssub_2<kill>
>
> It will also replace the TargetInstrInfo::copyRegToReg hook when copying virtual registers:
>
> %reg1050 = COPY %reg1044<kill>
>
&g...
2010 Jun 17
0
[LLVMdev] Loopinfo Analysis
Hi Hisham,
Most likely the basic blocks are the headers of two different loops. Try running viewCFG() on the function in question to see if this is the case.
Tom
----- Original Message -----
From: "Hisham Chowdhury" <hisham_chow at yahoo.com>
To: llvmdev at cs.uiuc.edu
Sent: Wednesday, June 16, 2010 7:22:00 PM GMT -05:00 US/Canada Eastern
Subject: [LLVMdev] Loopinfo Analysis
2010 Jun 16
2
[LLVMdev] Loopinfo Analysis
Hello,
I have a question regrading the analysis pass that generates loop info from an .ll code. My previous understanding was there will be just one loop header(in the loop info) for a particular loop. But, when i use isLoopHeader() member function from the loop info class I get 'true' return value for two different basic blocks. Note both basic blocks are loop conditional block(break
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...h = TokenFactor 0x88c8d00:1, 0x88c9ba0:1
SU(6): 0x88c9c28: ch = BEQ 0x88c9ba0, 0x88c8a08, 0x88ca710, 0x88ca778
Selected machine code:
bb20: 0x88c8140, LLVM BB @0x88bec48, ID#8:
%reg1047 = LUi <ga:flags.2176>
%reg1048 = LW 0, <fi#6>
%reg1049 = ADDiu %reg1047, <ga:flags.2176>
%reg1050 = ADDu %reg1049, %reg1048
%reg1051 = LBu 0, %reg1050
%reg1052 = ADDiu %ZERO, 0
BEQ %reg1051, %reg1052, mbb<cond_next46,0x88c8430>
Successors according to CFG: 0x88c8430 (#13) 0x88c8218 (#9)
Total amount of phi nodes to update: 0
Replacing.1 0x88c8d00: ch = TokenFactor 0x88c9540:1, 0x8...
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
...ruction could be replicated three times.
(before transformation)
%reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
(after transformation)
%reg1043<def> = LDR %reg1040, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
...
%reg1053<def> = LDR %reg1050, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
...
%reg1063<def> = LDR %reg1060, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
In this example, should mem:LD4[%uglygep10] be removed from the three
instructions so that passes run later will not use dependence information
that...
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
...>
%reg1035 = move %reg1036
%reg1037 = move 0
setcc %reg1033, %reg1037
if <>0 goto %disp(label shortcirc_done.1)
goto %disp(label shortcirc_next.1)
shortcirc_next.1 (0x8065c70, LLVM BB @0x8060278):
%reg1046 = phi %reg1032, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1050 = phi %reg1035, mbb<shortcirc_next.0.selectcont.selectcont,0x8065c10>
%reg1038 = move 1
setcc %reg1027, %reg1038
if v< goto %disp(label shortcirc_next.1.selecttrue)
%reg1077 = move 0
goto %disp(label shortcirc_next.1.selectcont)
shortcirc_next.1.selecttrue (0x8065cd0, LLVM BB @0x8063...