search for: prologepiloginsertion

Hi Dale, yes it's just stack alignment. Unfortunately your patch doesn't make any difference. Thanks for thinking about this, Duncan. On Friday 27 June 2008 19:51:00 Dale Johannesen wrote: > On Jun 27, 2008, at 3:11 AMPDT, Duncan Sands wrote: > > FAIL: test/CodeGen/X86/vec_shuffle-10.ll > > Failed with exit(1) at line 3 > > while running: llvm-as <

On Jun 27, 2008, at 3:11 AMPDT, Duncan Sands wrote: > FAIL: test/CodeGen/X86/vec_shuffle-10.ll > Failed with exit(1) at line 3 > while running: llvm-as < test/CodeGen/X86/vec_shuffle-10.ll | llc - > march=x86 -mattr=+sse2 | not grep {sub.*esp} > subl $16, %esp > subl $16, %esp > child process exited abnormally Is the code actually loading and storing

Running on x86-64 linux: FAIL: test/CodeGen/X86/vec_ins_extract.ll Failed with exit(1) at line 1 while running: llvm-as < test/CodeGen/X86/vec_ins_extract.ll | opt -scalarrepl -instcombine | llc -march=x86 -mcpu=yonah | not grep sub.*esp subl $16, %esp subl $16, %esp subl $16, %esp subl $16, %esp child process exited abnormally FAIL:

On Jun 30, 2008, at 9:25 AMPDT, Duncan Sands wrote: > Hi Dale, yes it's just stack alignment. Unfortunately > your patch doesn't make any difference. > > Thanks for thinking about this, > > Duncan. OK, the test is not quite right then. This doesn't happen on Darwin so I'm afraid you'll have to debug it. Perhaps testing for

Hi Dale, > OK, the test is not quite right then. This doesn't happen on Darwin > so I'm > afraid you'll have to debug it. Perhaps testing for > (RegInfo->needsStackRealignment(Fn) && > FFI->getObjectIndexEnd()!=0) > ? yes, that works - thanks! Since I have no idea what this is doing, is it ok if I leave it to you to commit it?

Hi all, Virtual ISAs such as WebAssembly and NVPTX use infinite virtual register sets instead of traditional phsyical registers. PrologEpilogInserter is run after register allocation and asserts that all virtuals have been allocated but doesn't otherwise depend on this if scavenging is not needed. We'd like to use the target-independent PEI code for WebAssembly, so we're proposing a

Hello, after some time I'm trying to build my code with the current CVS of LLVM, and have a problem. The mentioned file, around line 184, contains: if (FixedSlot == FixedSpillSlots+NumFixedSpillSlots) { // Nope, just spill it anywhere convenient. FrameIdx = FFI->CreateStackObject(RegInfo->getSpillSize(Reg)/8,

Vladimir Prus wrote: > What's the division by 8 for? Neither 'CreateStackObject' nor > 'getSpillAlignment' documentation say what units the size is, but > everywhere it's in bytes. In my specific case, 'getSplillAlignment' returns > 4, which becomes 0 after division. Oh, it looks that backends now should specify register size in bits. I've updated

hi, list, i am making a llvm compiler for shader-like programs. as we known, shader programs are short and have less function calls. i found that i have to save/restore callee-saved register(CSR) in prolog and epilog. because I can violate ABI from driver(c code) and shader, i plan to append the attribute 'noreturn' to all shader functions. in PrologEpilogInserter.cpp, you can find that

> On Dec 10, 2015, at 10:49 AM, Derek Schuff <dschuff at google.com> wrote: > > > > On Thu, Dec 10, 2015 at 10:13 AM Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > > I am tempted to think no, we don’t, but I don’t know the use cases. > What post-RA passes with want to run with virtual regs? > > The immediate

On Tue, May 12, 2009 at 11:55 PM, Chris Lattner <clattner at apple.com> wrote: > Dan, can you add IVUsers.cpp to the appropriate cmakefile? > > -chris > > > On May 12, 2009, at 10:54 PM, OvermindDL1 wrote: > >> On Tue, May 12, 2009 at 11:40 PM, Chris Lattner <clattner at apple.com> >> wrote: >>> >>> On May 12, 2009, at 10:24 PM,

To fix some problems with how condition registers are saved/restored for PowerPC, I need to override TargetRegisterInfo::hasReservedSpillSlot() in PPCRegisterInfo. I've had some difficulties because of the constness of the function, and I'm wondering what the best way to handle this would be. Essentially I need to add a field to PPCRegisterInfo, and modify that field in

Hi, I have a problem getting a properly aligned stack for my LLVM backend. I've asked about this previously, but unfortunately only now could try the suggested solution. For reference, here's the original message from me: http://mail.cs.uiuc.edu/pipermail/llvmdev/2004-July/001388.html And here's reply from Chris: http://mail.cs.uiuc.edu/pipermail/llvmdev/2004-July/001390.html The

I want to check debug output of "PrologEpilogInserter" machine pass, and I have seen in the code that there are various `DEBUG` macros added. However, there is no `-debug` option present for `llc` like it is for `opt`. Closest option I saw after seeing output of `llc --help-list` is `-verify-debug-info` but that does not give any output. Regards, Meet. -------------- next part

Hi Evan, Thanks for your feedback! 2009/1/7 Evan Cheng <evan.cheng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand,

Does not seem to be a straight error with LLVM itself, but rather the tools, linking issues, here are the errors: Opt: 30> Creating library R:\SDKs\llvm\trunk_VC8_building\lib\Debug\opt.lib and object R:\SDKs\llvm\trunk_VC8_building\lib\Debug\opt.exp 30>LLVMScalarOpts.lib(IndVarSimplify.obj) : error LNK2019: unresolved external symbol "public: bool __thiscall

On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand, ARMRegisterInfo.td should exclude the LR > register from the set of allocatable registers for functions that

> On Dec 10, 2015, at 9:39 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > > > ----- Original Message ----- >> From: "Quentin Colombet" <qcolombet at apple.com> >> To: "Derek Schuff" <dschuff at google.com> >> Cc: "Hal Finkel" <hfinkel at anl.gov>, llvm-dev at lists.llvm.org >> Sent: Wednesday, December

On Thu, Apr 9, 2009 at 4:34 PM, Anton Korobeynikov <anton at korobeynikov.info>wrote: > Hello, Aaron > > > How/where are function prologs and epilogs generated, is it bespoke C++ > code > > or TableGen generated ? > > > > If someone could point me in the right direction please. > Calling convention is really-really far from prologue/epilogue emission :)

...ter allocation means different things to different > people. The approach that is described on the open projects page is quite > simple; it still runs the register allocator on one function at a time. > > I am not aware of any papers describing this simple idea. > > Basically, the PrologEpilogInsertion pass will add a bit mask to > MachineModuleInfo describing which registers are clobbered by the function > being compiled. Later, when compiling the callers, that bit mask is used to > initialize the regmask operands on call instructions. > So the idea is to sidestep from the calling c...