search for: maintenance_interrupt

...arm/gic.c index 61de230..2674f84 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -723,6 +723,12 @@ int gicv_setup(struct domain *d) gic.vbase); } +static void gic_irq_eoi(void *info) +{ + int virq = (int) info; + GICC[GICC_DIR] = virq; +} + static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) { int i = 0, virq; @@ -733,6 +739,10 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r while ((i = find_next_bit((const long unsigned int *) &eisr, 64, i)) < 64) {...

...arm/gic.c index 61de230..feb7b29 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -723,6 +723,12 @@ int gicv_setup(struct domain *d) gic.vbase); } +static void gic_irq_eoi(void *info) +{ + int virq = (int) info; + GICC[GICC_DIR] = virq; +} + static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) { int i = 0, virq; @@ -733,6 +739,10 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r while ((i = find_next_bit((const long unsigned int *) &eisr, 64, i)) < 64) {...

...&iter->lr_link); + spin_unlock(&gic.lock); + return; + } + } + list_add(&n->lr_link, &gic.lr_pending); + spin_unlock(&gic.lock); + return; +} + void gic_inject_irq_start(void) { uint32_t hcr; @@ -435,13 +475,25 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r uint32_t lr; uint64_t eisr = GICH[GICH_EISR0] | (((uint64_t) GICH[GICH_EISR1]) << 32); - for ( i = 0; i < 64; i++ ) { + for ( i = 0; i < nr_lrs; i++ ) { if ( eisr & ((uint64_t)1 << i) ) { st...

...each_vcpu ( d, v ) + { + gic_dump_info(v); + } } long arch_do_vcpu_op(int cmd, struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 88f2d3a..9db1f57 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -677,6 +677,33 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r } } +void gic_dump_info(struct vcpu *v) +{ + int i; + struct pending_irq *p; + + printk("GICH_LRs (vcpu %d) mask=%llx\n", v->vcpu_id, v->arch.lr_mask); + if ( v == gic_running ) + { + for ( i = 0; i < nr...

...ic_init(void) { @@ -460,6 +532,9 @@ void __init gic_init(void) gic_hyp_init(); spin_unlock(&gic.lock); + + register_keyhandler(''G'', &dump_gic_keyhandler); + } void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) @@ -913,7 +988,7 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r } } -void gic_dump_info(struct vcpu *v) +void gic_dump_info_guest(struct vcpu *v) { int i; struct pending_irq *p; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 41f0b3b..e6369fa 100644 --- a/xen/include/asm-...

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See