search for: gic_spi

...0>; > + assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; > + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; > + assigned-clock-rates = <50000000>; > + reg = <0x8D80000 0x158>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; > + dmas = <&fdma0 2 0 1>; > + dai-name = "Uni Player #0 (HDMI)"; > + dma-names = "tx"; > + st,uniperiph-id = <0>; > + st,version = <5>; > + st,mode = "HDMI"; > + }; > + > + sti_uni_pl...

...0>; > + assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; > + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; > + assigned-clock-rates = <50000000>; > + reg = <0x8D80000 0x158>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; > + dmas = <&fdma0 2 0 1>; > + dai-name = "Uni Player #0 (HDMI)"; > + dma-names = "tx"; > + st,uniperiph-id = <0>; > + st,version = <5>; > + st,mode = "HDMI"; > + }; > + > + sti_uni_pl...

...clk_s_d0_flexgen CLK_PCM_0>; + assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; + assigned-clock-rates = <50000000>; + reg = <0x8D80000 0x158>; + interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; + dmas = <&fdma0 2 0 1>; + dai-name = "Uni Player #0 (HDMI)"; + dma-names = "tx"; + st,uniperiph-id = <0>; + st,version = <5>; + st,mode = "HDMI"; + }; + + sti_uni_player1: sti-uni-player at 1 { + compatible =...

...limcore", "dmem", "peripherals", "imem"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>; + dma-channels = <16>; + #dma-cells = <3>; + }; + + /* fdma app */ + fdma1: dma-controller at 8e40000 { + compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; + reg = <0x8e40000 0x8000>, + <0x8e50000 0x3000>, +...

...> + #sound-dai-cells = <0>; > + st,syscfg = <&syscfg_core>; > + reg = <0x8D83000 0x158>; We usually use lower-case for the address. Since this has a 'reg' property, the '0' in the node name does not look appropriate. > + interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; > + dmas = <&fdma0 5 0 1>; > + dma-names = "rx"; > + dai-name = "Uni Reader #0 (PCM IN)"; Oooo, not seen something like this before. If it does not already have one, it would require a DT Ack. > + st,version = <3>; Th...

...> + #sound-dai-cells = <0>; > + st,syscfg = <&syscfg_core>; > + reg = <0x8D83000 0x158>; We usually use lower-case for the address. Since this has a 'reg' property, the '0' in the node name does not look appropriate. > + interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; > + dmas = <&fdma0 5 0 1>; > + dma-names = "rx"; > + dai-name = "Uni Reader #0 (PCM IN)"; Oooo, not seen something like this before. If it does not already have one, it would require a DT Ack. > + st,version = <3>; Th...

...; st,mode = "SPDIF"; }; + + sti_uni_reader0: sti-uni-reader at 0 { + compatible = "st,sti-uni-reader"; + status = "disabled"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + reg = <0x8D83000 0x158>; + interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; + dmas = <&fdma0 5 0 1>; + dma-names = "rx"; + dai-name = "Uni Reader #0 (PCM IN)"; + st,version = <3>; + }; + + sti_uni_reader1: sti-uni-reader at 1 { + compatible = "st,sti-uni-reader"; + status = "disabled&quo...

...+ b/arch/arm/boot/dts/tegra124.dtsi @@ -102,6 +102,21 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + gpu at 0,57000000 { + compatible = "nvidia,gk20a"; + reg = <0x0 0x57000000 0x0 0x01000000>, + <0x0 0x58000000 0x0 0x01000000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "stall", "nonstall"; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + clock-names = "gpu", "pll"; +...

...+ See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - gpu + +Example: + +/ { + gpu at 0,57000000 { + compatible = "nvidia,gk20a"; + reg = <0x0 0x57000000 0x0 0x01000000>, + <0x0 0x58000000 0x0 0x01000000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "stall", "nonstall"; + vdd-supply = <&vdd_gpu>; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + clock-names...

...t;&syscfg_core>; > > + reg = <0x8D83000 0x158>; > > We usually use lower-case for the address. Will fix. > > Since this has a 'reg' property, the '0' in the node name does not > look appropriate. Will fix. > > > + interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; > > + dmas = <&fdma0 5 0 1>; > > + dma-names = "rx"; > > + dai-name = "Uni Reader #0 (PCM IN)"; > > Oooo, not seen something like this before. > > If it does not already have one, it would require a DT Ack. N...

This series adds support for probing platform devices on Nouveau, as well as the DT bindings for GK20A. It doesn't enable the GPU yet on Tegra boards since a few extra things need to be supported before that. Thanks to the input received for v1, this version is more self-contained and shares less stuff between nouveau_drm and nouveau_platform. The major change is that nouveau_platform is now

Hi Vinod, Bjorn, Patrice, This patchset adds support for the Flexible Direct Memory Access (FDMA) core found on STi chipsets from STMicroelectronics. The FDMA is a slim core CPU with a dedicated firmware. It is a general purpose DMA controller supporting 16 independent channels and data can be moved from memory to memory or between memory and paced latency critical real time targets. After quite

Hi Vinod, Bjorn, Patrice, This patchset adds support for the Flexible Direct Memory Access (FDMA) core found on STi chipsets from STMicroelectronics. The FDMA is a slim core CPU with a dedicated firmware. It is a general purpose DMA controller supporting 16 independent channels and data can be moved from memory to memory or between memory and paced latency critical real time targets. After quite

This patch series is the final (?) step towards the initial support of GK20A, allowing it to be probed and used (currently at a very slow speed, and for offscreen rendering only) on the Jetson TK1 and Venice 2 boards. The main piece if the first patch which adds platform devices probing support to Nouveau. There are probably lots of things that need to be discussed about it, e.g.: * The way the

This series adds support for probing platform devices on Nouveau, as well as the DT bindings for GK20A. It doesn't enable the GPU yet on Tegra boards since a few extra things need to be supported before that. This version is mostly identical to v2 but fixes an important issue: the drvdata must be set to the drm_device for sysfs to work, so the platform device structure now includes the