Displaying 7 results from an estimated 7 matches for "getphysicalregisterregclass".
2010 Jun 16
0
[LLVMdev] Simpler subreg ops in machine code IR
On Jun 15, 2010, at 2:48 PM, Jakob Stoklund Olesen wrote:
> I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
2007 Sep 05
1
[LLVMdev] Exception Problems
Hi Anton & Duncan,
When I try to compile on Darwin now, I get this:
$ /Volumes/Gir/devel/llvm/llvm-gcc-4.0.obj/gcc/xgcc <options> -o
eh_alloc.o
Assertion failed: (false && "Couldn't find the register class"),
function getPhysicalRegisterRegClass, file /Volumes/Gir/devel/llvm/
llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp, line 269.
../../../../../llvm-gcc-4.0.src/libstdc++-v3/libsupc++/eh_alloc.cc:
182: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://llv...
2010 Jun 15
4
[LLVMdev] Simpler subreg ops in machine code IR
I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
The COPY instruction handles subreg operations with less
2007 Jun 18
2
[LLVMdev] TargetRegisterClass for Physical Register
How do I get the TargetRegisterClass for a physical register?
SSARegMap::getRegClass only works for virtual registers.
-Dave
2007 Jun 19
0
[LLVMdev] TargetRegisterClass for Physical Register
Take a look at getPhysicalRegisterRegClass(
const MRegisterInfo *MRI,
MVT::ValueType VT,
unsigned reg)
in ScheduleDAG.cpp.
--
Christopher Lamb
On Jun 18, 2007, at 4:52 PM, David A. Greene wrote:
> How do I get the TargetRegisterClass for a physical register?
> SSARegMap::getRegClass only works for virt...
2007 Jun 19
3
[LLVMdev] TargetRegisterClass for Physical Register
On Monday 18 June 2007 19:02, Christopher Lamb wrote:
> Take a look at getPhysicalRegisterRegClass(
> const MRegisterInfo *MRI,
> MVT::ValueType VT,
> unsigned reg)
>
> in ScheduleDAG.cpp.
Yuck. I was afraid of that.
What is the ValueType needed for? Isn't the register id itself an indication
of the ValueType it represents? Where I'm at I do...
2009 Jul 17
0
[LLVMdev] Running all the backends over test/CodeGen/Generic
...ollowing is the
remaining issues:
x86-64: 3. I'm not entirely sure what's going on here, since the
buildbot should be running this. The assertion is the following:
llc: /home/eli/llvm/lib/Target/TargetRegisterInfo.cpp:59: virtual
const llvm::TargetRegisterClass*
llvm::TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned int,
llvm::MVT) const: Assertion `BestRC && "Couldn't find the register
class"' failed.
x86-32: 0.
Sparc: 6. Caused by Sparc overriding LowerArguments instead of using
the normal lowering for arguments, leading to bad interactions with
illegal types.
PPC64: 0....