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...be recorded in a specific folder A,B,C,D or E. then this 4 digit number is mailed ( can be done easily ). On pressing 2 at main ivr, read 4 digits and play back the corresponding file from given 5 directories. What is the easiest way to get this done ? Php agi or just dialplan hacks ? How can i geenrate a 4 digit unique pin each time for the file ? TIA. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.digium.com/pipermail/asterisk-users/attachments/20091023/83f62328/attachment.htm

I'm about to replace my old server. Both servers are on my internal network. The old one ist running debian lenny(32bit) with dovecot 1.0.15 and the new one debian Wheezy with dovecot 2.1.7. I set up the users on both systems identically (same gid uid). My first attempt was tho simply rsync the Maildirs along with the homes. Both deovecot versions are set up with the maildir format, but this

I'm having a problem when generating the following LLVM intrinsics: @llvm.exp2.f32 @llvm.log2.f32 On linux, these are available on as part of standard math libraries, the code geenrator expands them into library calls, and the linker happily finds them. However, on Windows and OSX, where no implementation exists, instead of throwing a runtime error, we get a call to a function with a null pointer. It ends up looking like this: mov eax, 0 call eax Would it be possible to add...

flight 12988 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/12988/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: build-i386-oldkern 4 xen-build fail REGR. vs. 12979 Regressions which are regarded as allowable (not blocking): test-amd64-amd64-xl-qemuu-win7-amd64 12

...real world, or even had CodeGen go wrong in a way that *could* > do so outside the -O0 situation. That's true as long as the "Exclusives Reservation Granule" == 1 cache-line and you don't deterministically cause the reservation to be cleared in some other way: e.g. repeatable geenrating a conflict miss or triggering a trap etc. I don't think any Arm cores ship with direct-mapped caches so I'll admit this is unlikely. The possibility for issues increases if the Exclusives Reservation Granule is larger. For the Cortex-M4, the ERG is the entire address range <http://in...

# RFC: Atomic LL/SC loops in LLVM revisited ## Summary This proposal gives a brief overview of the challenges of lowering to LL/SC loops and details the approach I am taking for RISC-V. Beyond getting feedback on that work, my intention is to find consensus on moving other backends towards a similar approach and sharing common code where feasible. Scroll down to 'Questions' for a summary