search for: createreg

...on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. For the def-operand, with a subregindex, an implicit-use operand was added with this code: VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); MI.addOperand(MachineOperand::CreateReg(VirtReg, false, // isDef true)); // isImplicit As, can be seen, it is presumed that this operand is always the last operand, this is however not the case. It in fact becomes the first of the impl-use ope...

Is it possible to get a virtual register and then use that to create a real register? I've seen it done in unittests/CodeGen/MachineInstrTest.cpp like this: unsigned VirtualDef1 = -42; VD1VU->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); But when I do that in my code I get an assertion so I wasn't sure if it's legal or not. Thanks. ________________________________ From: David Greene <dag at cray.com> Sent: Wednesday, January 2, 2019 9:23 AM To: m m Cc: via llvm-dev Subject: Re: [llvm-...

...me"); llvm::MCSymbol* mcs = Ctx.getOrCreateSymbol(tname); Str->EmitLabel(mcs); Or even something more complicated like setting up an MCInst and all it's operands: llvm::MCInst *llinst = new MCInst(); llinst->setOpcode(input_opcode); llinst->addOperand(llvm::MCOperand::createReg(input_reg0)); llinst->addOperand(llvm::MCOperand::createReg(input_reg1)); const llvm::Twine tname("label_name"); const llvm::MCSymbol* mcs = Ctx.getOrCreateSymbol(tname); const llvm::MCSymbolRefExpr *msre = llvm::MCSymbolRefExpr::create(mcs, Ctx); llinst->addOperand(llvm::...

...1InstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI), RI(STI) { } /// getNoopForMachoTarget - Return the noop instruction to use for a noop. void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { NopInst.setOpcode(ARM::tMOVr); NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); NopInst.addOperand(MCOperand::CreateReg(0)); } unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { return 0; } void Thumb1InstrInfo::copyPhysReg(Mach...

...d two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. > > For the def-operand, with a subregindex, an implicit-use operand was added with this code: > > VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); > MI.addOperand(MachineOperand::CreateReg(VirtReg, > false, // isDef > true)); // isImplicit > > As, can be seen, it is presumed that this operand is always the last operand, this is however not the case. It in fact becomes the first...

On Tue, Apr 08, 2014 at 04:08:13PM +0400, Robert Khasanov wrote: > Hi Reid, > > Would you approve your patches r203146 and r202774 to be backported to > 3.4.1? They fix stability issues in x86 asm. > Hi Robert, I was able to merge r203146, but it used a c++11 feature: std::string::back() which I replaced with std::string::at(std::string::size() - 1). r202774 was not merged,

...0x00007f2d54c26340 4 libc.so.6 0x00007f2d53e62f79 gsignal + 57 5 libc.so.6 0x00007f2d53e66388 abort + 328 6 libc.so.6 0x00007f2d53e5be36 7 libc.so.6 0x00007f2d53e5bee2 8 llc 0x00000000009be707 9 llc 0x0000000000cfed54 llvm::FunctionLoweringInfo::CreateReg(llvm::MVT) + 64 10 llc 0x0000000000cfeebd llvm::FunctionLoweringInfo::CreateRegs(llvm::Type*) + 337 11 llc 0x0000000000cf33fa 12 llc 0x0000000000cfe4cb llvm::FunctionLoweringInfo::set(llvm::Function const&, llvm::MachineFunction&, llvm::SelectionDAG*) + 2...

...-- > LLVM C++ code I tried to translate this to: > /* 1 mov (%gs), %r14 */ > MachineInstrBuilder e1 = > BuildMI(MBB,MBB.end(),DL,TII->get(X86::MOV64rm),X86::R14) > .addReg(X86::GS); > /* 2 mov %r15, %gs:0x0(%r14) */ > MachineOperand baseReg = MachineOperand::CreateReg(X86::GS,false); > MachineOperand scaleAmt = MachineOperand::CreateImm(0x1); > MachineOperand indexReg = MachineOperand::CreateReg(X86::R14,false); > MachineOperand disp = MachineOperand::CreateImm(0x0); > > BuildMI(MBB, MBB.end(), DL, TII->get(X86::MOV64mr)) >...

The size suffix thing is a weird quirk in our assembler I should look into fixing. Instructions in at&t syntax usually have a size suffix that is often optional For example: add %ax, %bx and addw %ax, %bx Are equivalent because the register name indicates the size. but for an instruction like this addw $1, (%ax) There is nothing to infer the size from so an explicit suffix is

Hi, I'm new to LLVM. I'd like to know if there is a method I can call whenever I need any available CPU register. Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20181222/e916b214/attachment.html>

...on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. For the def-operand, with a subregindex, an implicit-use operand was added with this code: VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); MI.addOperand(MachineOperand::CreateReg(VirtReg, false, // isDef true)); // isImplicit As, can be seen, it is presumed that this operand is always the last operand, this is however not the case. It in fact becomes the first of the impl-use ope...

...ic: explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {} /// addReg - Add a new virtual register operand... /// const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0, unsigned SubReg = 0) const { MI->addOperand(MachineOperand::CreateReg(RegNo, flags & RegState::Define, flags & RegState::Implicit, flags & RegState::Kill, flags & RegState::...

Fernando, The code there should be more or less functional, though it's not currently used by anything. Eventually it should probably be moved to a method on MachineBasicBlock. The API breakage you're seeing is because some methods moved around. Feel free to fix it. :-) --Owen On Jan 26, 2008, at 6:31 PM, Fernando Magno Quintao Pereira wrote: > > Hi LLVMers, > >

Hi LLVMers, what is the status of breaking critical edges in machine functions? I just compiled the top of the LLVM tree, and I found llvm/CodeGen/BreakCriticalMachineEdge.h. But this file seems not to be up-to-date with the other classes in the top of the tree. For instance, it calls isTerminatorInstr on llvm::TargetInstrInfo, but this method is no longer there. If I want to break

...{ // If this is a segment register followed by a ':', then this is the start // of a memory reference, otherwise this is a normal register reference. - if (getLexer().isNot(AsmToken::Colon)) + if (Parser->getLexer().isNot(AsmToken::Colon)) return X86Operand::CreateReg(RegNo, Start, End); - getParser().Lex(); // Eat the colon. + Parser->Lex(); // Eat the colon. return ParseMemOperand(RegNo, Start); } case AsmToken::Dollar: { // $42 -> immediate. - SMLoc Start = Parser.getTok().getLoc(), End; - Parser.Lex(); + SMLoc...