Displaying 10 results from an estimated 10 matches for "clrc".
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clr
2008 Jul 14
1
Off topic: Tcl/Tk outside R.
...th Tcl/Tk *outside*
of R to see if I could get the hang of just what Tcl/Tk actually is.
(As I said I am floundering; I can't seem to get a conceptual grip on
what it's all about.) I discovered a Tcl/Tk ``Cookbook'' by Sastry
and Sastry that looked promising. URL:
http://www.dci.clrc.ac.uk/Publications/Cookbook/
Tried the first couple of (ultra-simple) examples and they seemed to
work.
(Amazing, for me.)
Then I tried the example on creating an executable file for invoking
the Tcl/Tk commands. The instructions said to create a file
``button.tcl'' with a first line...
2008 Jul 16
0
security=server authentication via vista
...it is defaulting to user
authentication. Does anybody know if the settings I am using are
correct, or could there be another reason that I don't go straight to my
linux share.
I get no problems connecting using this set up from my XP box.
Thanks for any help,
Stephen
[global]
workgroup = CLRC
server string = Samba Server
hosts allow = 130.246.40. 130.246.41. 130.246.42. 130.246.43.
130.246.44. 130.246.47.
printcap name = /etc/printcap
log level = 10
log file = /var/log/samba/smbd.log
max log size = 50
;------------------
lanman auth = no
ntlm auth = no
ntlmv2 auth = ye...
2006 Jan 18
1
Powell's unconstrained derivative-free nonlinear least squares routine, VA05AD
...o this end, I recently enquired of the custodians of the HSL whether it would be possible to make it freely available to the R community. The answer was basically 'yes'. Would anybody be willing to port it across? I am not sufficiently capable of doing this yet.
HSL Archive: http://www.cse.clrc.ac.uk/nag/hsl/contents.shtml
===================
Dr D G Kinniburgh
British Geological Survey
Crowmarsh Gifford
Wallingford
OX10 8BB
UK
Phone: 0044 1491 692293
Fax: 0044 1491 692345
email: dgk_at_bgs.ac.uk
2019 Nov 13
2
[AVR] [MSP430] Code gen improvements for 8 bit and 16 bit targets
...signext i16 @isNotNegativeUsingCmp(i16 signext %x) {
%cmp = icmp sgt i16 %x, -1
%r = zext i1 %cmp to i16
ret i16 %r
}
And compile that for MSP430:
$ ./llc -o - -mtriple=msp430 shift.ll
isNotNegativeUsingShift: ; @isNotNegativeUsingShift
; %bb.0:
inv r12
swpb r12
mov.b r12, r12
clrc
rrc r12
rra r12
rra r12
rra r12
rra r12
rra r12
rra r12
ret
isNotNegativeUsingCmp: ; @isNotNegativeUsingCmp
; %bb.0:
mov r12, r13
mov #1, r12
tst r13
jge .LBB1_2
; %bb.1:
clr r12
.LBB1_2:
ret
How do you intend to optimize code that is written in the 1st form? Or is
that not allow...
2019 Nov 14
2
[AVR] [MSP430] Code gen improvements for 8 bit and 16 bit targets
...= icmp sgt i16 %x, -1
> %r = zext i1 %cmp to i16
> ret i16 %r
> }
>
> And compile that for MSP430:
> $ ./llc -o - -mtriple=msp430 shift.ll
> isNotNegativeUsingShift: ; @isNotNegativeUsingShift
> ; %bb.0:
> inv r12
> swpb r12
> mov.b r12, r12
> clrc
> rrc r12
> rra r12
> rra r12
> rra r12
> rra r12
> rra r12
> rra r12
> ret
>
> isNotNegativeUsingCmp: ; @isNotNegativeUsingCmp
> ; %bb.0:
> mov r12, r13
> mov #1, r12
> tst r13
> jge .LBB1_2
> ; %bb.1:
> clr r12
> .LBB1_2:
>...
2019 Sep 30
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...t; %a.lobit = lshr i32 %a, 31
> %0 = trunc i32 %a.lobit to i16
> %.not = xor i16 %0, 1
> ret i16 %.not
> }
>
> The backend then turns this into the following totally suboptimal code:
>
> cmpge32_0:
> mov r13, r12
> inv r12
> swpb r12
> mov.b r12, r12
> clrc
> rrc r12
> rra r12
> rra r12
> rra r12
> rra r12
> rra r12
> rra r12
> ret
> .Lfunc_end0:
> .size cmpge32_0, .Lfunc_end0-cmpge32_0
>
>
> The cause of this anomaly is again the presence of the Shift instruction (%a.lobit
> = lshr i32 %a, 31) at the IR level...
2019 Oct 01
3
[cfe-dev] CFG simplification question, and preservation of branching in the original code
....lobit = lshr i32 %a, 31
> %0 = trunc i32 %a.lobit to i16
> %.not = xor i16 %0, 1
> ret i16 %.not
> }
>
> The backend then turns this into the following totally suboptimal code:
>
> cmpge32_0:
> mov r13, r12
> inv r12
> swpb r12
> mov.b r12, r12
> clrc
> rrc r12
> rra r12
> rra r12
> rra r12
> rra r12
> rra r12
> rra r12
> ret
> .Lfunc_end0:
> .size cmpge32_0, .Lfunc_end0-cmpge32_0
>
>
> The cause of this anomaly is again the presence of the Shift instruction (%a.lobit = lshr i32 %a, 31) at the IR...
2019 Sep 30
3
[cfe-dev] CFG simplification question, and preservation of branching in the original code
On Mon, Sep 30, 2019 at 11:52 AM Joan Lluch <joan.lluch at icloud.com> wrote:
>
> Hi Roman,
>
> Is "test" actually an implementation of a 64-bit-wide multiplication
> compiler-rt builtin?
> Then i'd think the main problem is that it is being optimized in the
> first place, you could end up with endless recursion…
>
>
> No, this is not a compiler-rt
2019 Nov 13
2
[AVR] [MSP430] Code gen improvements for 8 bit and 16 bit targets
On Wed, Nov 13, 2019 at 12:26 PM Joan Lluch via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
>
> Hi All,
>
> In relation to the subject of this message I got my first round of patches successfully reviewed and committed. As a matter of reference, they are the following:
>
> https://reviews.llvm.org/D69116
> https://reviews.llvm.org/D69120
>
2019 Oct 03
2
[cfe-dev] CFG simplification question, and preservation of branching in the original code
...a.lobit to i16
>> %.not = xor i16 %0, 1
>> ret i16 %.not
>> }
>>
>> The backend then turns this into the following totally suboptimal code:
>>
>> cmpge32_0:
>> mov r13, r12
>> inv r12
>> swpb r12
>> mov.b r12, r12
>> clrc
>> rrc r12
>> rra r12
>> rra r12
>> rra r12
>> rra r12
>> rra r12
>> rra r12
>> ret
>> .Lfunc_end0:
>> .size cmpge32_0, .Lfunc_end0-cmpge32_0
>>
>>
>> The cause of this anomaly is again the presence of the Shif...