search for: bsr

..." (and the same for 64-bit version). "sizeof(FLAC__uint32) * CHAR_BIT" must be 32, or the code won't work. So it's simpler to use "31 - FLAC__clz_uint32(v)" or even better, "FLAC__clz_uint32(v) ^ 31". Why XORing is better: gcc implements __builtin_clz as bsr^31, so FLAC__bitmath_ilog2() now calculates 31 - (bsr^31). GCC is unable to simplify it to just bsr. But it can do it for (bsr^31)^31. 5) The patch adds FLAC__U64L() for a big constant. -------------- next part -------------- A non-text attachment was scrubbed... Name: 2_bitmath_h.patch Type: app...

Hello, just trying to use the dragonegg plugin with gcc on my project. Unfortunately I get an /usr/local/lib/gcc/x86_64-unknown-linux-gnu/4.5.2/include/ia32intrin.h:170:35: error: unsupported target builtin ‘__builtin_ia32_bsrdi’ used error. I use (and need) the "bsr" (bit scan reverse) instruction. So it seems it isn't implemented (yet). Can I safely use gcc inline assembly instead? Are the some preprocessor macros defined while using dragonegg so that I can conditionally compile? - Gunther

Hi I'm a new user of Asterisk and made the first VoIP call on my own LAN with a good quality. Now I want to configure a CMTS (motorola BSR 1000) and a server to support QoS. Does anyone knows how to configure this in order to work with SIP and with Asterisk? any ideas or tutorials? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.digium.com/pipermail/asterisk-users/attachments/200604...

..._wide() from FLAC__uint64 to unsigned long. The type of idx variable inside FLAC__bitmath_ilog2() was also changed (from FLAC__uint32 to unsigned long), for symmetry. 2. FLAC__clz_uint32() returns the result of BitScanReverse() XOR 31. FLAC__bitmath_ilog2() returns 31-FLAC__clz_uint32() == 31-(BSR^31). As 0<=BSR<=31 so 31-(BSR^31) == BSR. But I don't think that compilers are so smart that can optimize this expression. So it is better to change FLAC__bitmath_ilog2() so it simply calls BitScanReverse() when possible. 3. FLAC__bitmath_ilog2_wide() cannot be compiled with MSVC: it...

...'s a bug I would not call that a bug, just a result of trying to write cross platform code and relying on functions that are not specified by any standard. > 2. FLAC__clz_uint32() returns the result of BitScanReverse() XOR 31. > FLAC__bitmath_ilog2() returns 31-FLAC__clz_uint32() == 31-(BSR^31). > > As 0<=BSR<=31 so 31-(BSR^31) == BSR. But I don't think that compilers > are so smart that can optimize this expression. So it is better to change > FLAC__bitmath_ilog2() so it simply calls BitScanReverse() when possible. I want to look at this more carefully. Its pr...

These instructions are prefix selected flavors of bsf and bsr respectively, and hence the presences of the F3 prefix must be handled in the emulation code in order to avoid running into problems on newer CPUs. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -10...

Dear list, I have a series of data points which I want to approximate with exactly two linear functions. I would like to choose the intervals so that the total deviation from my fitted lines is minimal. How do I best do this? Thanks! Kamila The information transmitted in this electronic communication...{{dropped}}

...re storeRegToStackSlot and make it available again at the > > point of earlier use? > > > > > > > Typical solution is to either reserve a register for these purposes so > the backend does not have to worry about its value being clobbered. We have only one register (BSR) which we need to set correctly before every load/store. Setting up this register is done via an operation called 'banksel'. The problem is that spill/reload gets in between a banksel and load/store operation; and these spill/reload also modify BSR. Regalloc fails to recognize this and d...

...all, Some non trivial legalization of operations which aren't supported by the backend would benefit from having the optimizer pass on them. I noticed some example trying to optimize various pieces of code over the past weeks. One offender is the cttz/ctlz intrinsic when defined on 0. On X86, BSR and NSF are undefined on 0, and only recent CPU have the LZCNT and TZCNT instructions that are properly defined for 0. The backend insert code with a branch that checks for 0 and use bsf/bsr or just use a constant. But if we are to branch anyway, and one path of the branch set the value as a const...

...zation of operations which aren't supported by > the backend would benefit from having the optimizer pass on them. I noticed > some example trying to optimize various pieces of code over the past weeks. > > > > One offender is the cttz/ctlz intrinsic when defined on 0. On X86, BSR > and NSF are undefined on 0, and only recent CPU have the LZCNT and TZCNT > instructions that are properly defined for 0. The backend insert code with > a branch that checks for 0 and use bsf/bsr or just use a constant. > > > > But if we are to branch anyway, and one path of t...

On Oct 22, 2008, at 11:09 AM, Sanjiv.Gupta at microchip.com wrote: > In our case, storeRegToStackSlot, loadRegFromStackSlot clobbers some > other physical register which may be holding a live value used > somewhere else. How do I make regalloc aware so that it saves the > value before storeRegToStackSlot and make it available again at the > point of earlier use? >

In our case, storeRegToStackSlot, loadRegFromStackSlot clobbers some other physical register which may be holding a live value used somewhere else. How do I make regalloc aware so that it saves the value before storeRegToStackSlot and make it available again at the point of earlier use? TIA, Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL:

El 03/05/12 12:19, Miroslav Lichvar escribi?: > Hi Josh, > > nice to see you here again. > > On Wed, Apr 25, 2012 at 04:26:05PM -0700, Josh Coalson wrote: >> (Jumping in again, maybe at the wrong point since this doesn't seem >> to involve encoding, but here goes.) >> >> Miroslav's patches have always been high-quality for sure. But >>

...b smb_rcls=0 smb_reh=0 smb_err=0 smb_flg=24 smb_flg2=49219 smb_tid=65535 smb_pid=65279 smb_uid=0 smb_mid=65534 smt_wct=1 smb_vwv[ 0]= 1 (0x1) smb_bcc=12 [2006/09/26 16:19:51, 10] lib/util.c:dump_data(2053) [000] 4A 6C 4A 6D 49 68 43 6C 42 73 72 00 JlJmIhCl Bsr. [2006/09/26 16:19:51, 3] smbd/process.c:switch_message(900) switch message SMBecho (pid 23178) conn 0x0 [2006/09/26 16:19:51, 3] smbd/sec_ctx.c:set_sec_ctx(288) setting sec ctx (0, 0) - sec_ctx_stack_ndx = 0 [2006/09/26 16:19:51, 5] auth/auth_util.c:debug_nt_user_token(452) NT user token: (N...

Hi, Is it possible to produce box-and-whisker plots given that I have the median, interquartile and 5/95th centile values, but not the data from which they come? It seems that it ought to be possible to coerce bxp to do what I want, but I can't quite see how. Thanks, Matthew -- Matthew Vernon, Research Fellow Ecology and Epidemiology Group, University of Warwick

Hi All, I've seen several variations on this topic, but nothing exactly the same: I have two Windows 2003 servers that I want to use rsync (2.6.8) to mirror. These machines are separated by a WAN. Initial attempts to get rsync working between them have not been successful. The first rsync went fine, which seeded the files, but the second sync always fails (at a ramdom time) with a

...vm/obj/../test/Regression/CodeGen/Alpha/dg.exp ... FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll: NODE: 0x8582a40: i32,ch = CopyFromReg 0x8582980:1, 0x85829c0 Abort trap (core dumped) FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/bsr.ll: NODE: 0x85823c0: i32,ch = CopyFromReg 0x8582300, 0x8582340 Abort trap (core dumped) FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/ctlz.ll: NODE: 0x8582340: i8,ch = CopyFromReg 0x8582280, 0x85822c0 Abort trap (core dumped) FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/Co...

...ows share from a laptop running XPpro, Samba won't accept the user neither for the homedirs nor for the datashare. So the big question is: where did I screw up and/or what did i forget? This is what my smb.conf looks like at the the moment: [global] workgroup = PROTEC realm = BSR.PROTEC-ENTERPRISES.COM password server = dc01-v.bsr.protec-enterprises.com preferred master = no server string = Samba FileServer Version %v netbios name = SAMBA-V # logs split per machine log file = /var/log/samba/%m.log # max 50KB per log f...

...__uint32 v) { /* Never used with input 0 */ #if defined(__INTEL_COMPILER) - return _bit_scan_reverse(n) ^ 31U; + return _bit_scan_reverse(v) ^ 31U; #elif defined(__GNUC__) && (__GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)) /* This will translate either to (bsr ^ 31U), clz , ctlz, cntlz, lzcnt depending on * -march= setting or to a software rutine in exotic machines. */ -- 1.7.10.4 --=_vA9B0g0mKp5QbmIrcmD4lw5 Content-Type: text/x-diff; charset=us-ascii; name=0002-bitwriter.c-Add-missing-extern-declaration.patch Content-Disposition: attachment; file...

...0000000 +0400 +++ b\src\libFLAC\include\private\bitmath.h 2013-08-14 10:20:51.484053700 +0400 @@ -78,12 +78,12 @@ return _bit_scan_reverse(v) ^ 31U; #elif defined(__GNUC__) && (__GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)) /* This will translate either to (bsr ^ 31U), clz , ctlz, cntlz, lzcnt depending on - * -march= setting or to a software rutine in exotic machines. */ + * -march= setting or to a software routine in exotic machines. */ return __builtin_clz(v); #elif defined(_MSC_VER) && (_MSC_VER >= 1400) - FLAC__uint32 idx; +...