Displaying 10 results from an estimated 10 matches for "amt2".
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amt
2007 Jan 25
3
Sum multiple columns individually
Can you sum a few columns at a time?
I tried
x =Calc.find(:all, :select => "sum(amt1) amt1, sum(amt2) amt2"
:conditions => ["where date > ?", date] )
The sql seems to function properly, but I wasn''t able to grab the
values. These just failed
x.amt1
x.send("amt1")
I tried changing up the query to use
sum(amt1) as amt1
sum(amt1) ''amt1''...
2017 Sep 15
2
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...ue,
SDNPVariadic]>;
def MYret : SDNode<"MYISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInGlue,
SDNPVariadic]>;
let hasCtrlDep = 1, hasSideEffects = 1 in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(MYCallseqStart timm:$amt1,
timm:$amt2)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(MYCallseqEnd timm:$amt1, timm:$amt2)]>;
}
def: Pat<(MYret), (JMP_Ret (i32 LR))>;
The f...
2017 Sep 15
0
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...def MYret : SDNode<"MYISD::RET_FLAG", SDTNone,
> [SDNPHasChain, SDNPOptInGlue,
> SDNPVariadic]>;
>
> let hasCtrlDep = 1, hasSideEffects = 1 in {
> def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
> [(MYCallseqStart timm:$amt1,
> timm:$amt2)]>;
> def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
> [(MYCallseqEnd timm:$amt1, timm:$amt2)]>;
> }
>
> def: Pat<(MYre...
2017 Sep 19
1
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
...SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
let hasCtrlDep = 1,
hasSideEffects = 1,
isCodeGenOnly = 1,
Defs = [SP],
Uses = [SP] in {
def ADJCALLSTACKDOWN : Pseudo<(outs),
(ins i32imm:$amt1, i32imm:$amt2),
[(MyCallseqStart timm:$amt1, timm:$amt2)]>;
def ADJCALLSTACKUP : Pseudo<(outs),
(ins i32imm:$amt1, i32imm:$amt2),
[(MyCallseqEnd timm:$amt1, timm:$amt2)]>;
}
def Custom_CALL : Pseudo...
2013 Oct 17
1
Reshape
...013","12/01/2012","12/01/2012")
df <- data.frame(Person,Amount,Date)
I would like to transpose the Amount data so that I can get the total amount paid by person and date.
So, it would look something like:
##Want it to look like:
Person Date Amt1 Amt2
1 12/01/2012 100 10
1 01/01/2013 100 10
1 02/01/2013 100 10
2 12/01/2012 50 150
I have been working with reshape, but I am having trouble getting it to look exactly right.
Thank you,
K
2009 Dec 01
4
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
...p;&
"Expanded integer type size not a power of two!");
DebugLoc dl = N->getDebugLoc();
// Get the incoming operand to be shifted.
SDValue InL, InH;
GetExpandedInteger(N->getOperand(0), InL, InH);
SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
Amt, NVBitsNode, ISD::SETULT);
SDValue Lo1, Hi1, Lo2, Hi2;
switch (N->getOpcode()) {
default: llvm_unreachable("Unknown shift");
case...
2009 Dec 01
0
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
On Mon, Nov 30, 2009 at 7:22 PM, Javier Martinez <javier at jmartinez.org> wrote:
> Hello,
>
> I'm working in adding support for 64-bit integers to my target. I'm using
> LLVM to decompose the 64-bit integer operations by using 32-bit registers
> wherever possible and emulating support where not. When looking at the bit
> shift decomposition I saw what seems to be a
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...etNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
- return true;
- }
- }
-
- // If we know that the high bits of the shift amount are all zero, then we can
- // do this as a couple of simple shifts.
- if ((KnownZero & Mask) == Mask) {
- // Compute 32-amt.
- SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
- DAG.getConstant(NVTBits, Amt.getValueType()),
- Amt);
-
- // Expand the incoming operand to be shifted, so that we have its parts
- SDValue InL, InH;
- ExpandOp(Op, InL, InH);...