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...ot;id"=>"3", "description"=>"I like to go in for sport"} } ------------------------------- This is the controller ------------------------------- def edit @editintersts = Interest.find_all if @request.post? Interest.update_all(params[:interest]) #__The problem is here__ end end -- Posted via http://www.ruby-forum.com/.

...106<def> = TFRI 16777216; IntRegs:%vreg106 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] IntRegs:%vreg37 This is not caught at this time, and only much later, when another instruction is scheduled to __the same slot___ the old one "occupied" (48B), the discrepancy is caught by one of unrelated asserts... I think at that time there are simply some stale aliases in liveness table. I'm going to continue with this tomorrow, but if this helps to identify a lurking bug today, my day was wort...

...ocal-part (SMTP Extensions may explicitly specify case-sensitive elements). That is, a command verb, an argument value other than a mailbox local-part, and free form text MAY be encoded in upper case, lower case, or any mixture of upper and lower case with no impact on its meaning. __The local-part of a mailbox MUST BE treated as case sensitive.__ Therefore, SMTP implementations MUST take care to preserve the case of mailbox local-parts. In particular, for some hosts, the user "smith" is different from the user "Smith". However, exploiting the cas...

...t; 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] > IntRegs:%vreg37 > > This is not caught at this time, and only much later, when another > instruction is scheduled to __the same slot___ the old one "occupied" > (48B), > the discrepancy is caught by one of unrelated asserts... I think at that > time there are simply some stale aliases in liveness table. > > I'm going to continue with this tomorrow, but if this helps to identify a > lurki...

Dear all, I'm working on a project that links to the BH package (http://cran.r-project.org/web/packages/BH/index.html). My packages doesn't call entry points which might terminate R nor write to stdout/stderr instead of to the console. However, it seems some of the codes in the BH package might. At any rate, when I include some boost headers such as boost/math/distributions/ through BH,

...16777216; IntRegs:%vreg106 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] IntRegs:%vreg37 This is not caught at this time, and only much later, when another instruction is scheduled to __the same slot___ the old one "occupied" (48B), the discrepancy is caught by one of unrelated asserts... I think at that time there are simply some stale aliases in liveness table. I'm going to continue with this tomorrow, but if this helps to identify a lurking bug today, my day was wort...

On 2017-04-25 15:50, Dirk Eddelbuettel wrote: > > On 25 April 2017 at 14:58, G?ran Brostr?m wrote: > | hello, > | > | I just installed R-3.4.0 from scratch: > | > | $ sudo apt install r-base > | > | but when I try > | > | > library(survival, lib.loc = "/usr/lib/R/library") > | > fit <- coxph(Surv(exit, event) ~ x, data = mort) > | > |

...; IntRegs:%vreg106 > 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] > IntRegs:%vreg37 > > This is not caught at this time, and only much later, when another > instruction is scheduled to __the same slot___ the old one "occupied" > (48B), the discrepancy is caught by one of unrelated asserts... I think > at that time there are simply some stale aliases in liveness table. > > I'm going to continue with this tomorrow, but if this helps to identify > a lurking b...

...16777216; IntRegs:%vreg106 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] IntRegs:%vreg37 This is not caught at this time, and only much later, when another instruction is scheduled to __the same slot___ the old one "occupied" (48B), the discrepancy is caught by one of unrelated asserts... I think at that time there are simply some stale aliases in liveness table. I'm going to continue with this tomorrow, but if this helps to identify a lurking bug today, my day was wort...

...%vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 >> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] >> IntRegs:%vreg37 >> >> This is not caught at this time, and only much later, when another >> instruction is scheduled to __the same slot___ the old one "occupied" >> (48B), the discrepancy is caught by one of unrelated asserts... I think >> at that time there are simply some stale aliases in liveness table. >> >> I'm going to continue with this tomorrow, but if this helps to identify &...

On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote: > > I've described that issue (see below) when you were out of town... I think > I am getting more context on it. Please take a look... > > So, in short, when the new MI scheduler performs move of an instruction, it > does something like this: > > // Move the instruction to its new

...Y %D2<kill>; DoubleRegs:%vreg29 > >> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] > >> IntRegs:%vreg37 > >> > >> This is not caught at this time, and only much later, when another > >> instruction is scheduled to __the same slot___ the old one > "occupied" > >> (48B), the discrepancy is caught by one of unrelated asserts... I > >> think at that time there are simply some stale aliases in liveness > table. > >> > >> I'm going to continue with this tomorrow, b...

...t; 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] > IntRegs:%vreg37 > > This is not caught at this time, and only much later, when another > instruction is scheduled to __the same slot___ the old one "occupied" > (48B), > the discrepancy is caught by one of unrelated asserts... I think at that > time there are simply some stale aliases in liveness table. > > I'm going to continue with this tomorrow, but if this helps to identify a > lurki...

Andy, I've described that issue (see below) when you were out of town... I think I am getting more context on it. Please take a look... So, in short, when the new MI scheduler performs move of an instruction, it does something like this: // Move the instruction to its new location in the instruction stream. MachineInstr *MI = SU->getInstr(); if (IsTopNode) {