Displaying 6 results from an estimated 6 matches for "1168b".
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1168
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...OPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28
register: %vreg3 replace range with [304r,320r:1) RESULT: [304r,320r:1)[320r,416r:0) 0 at 320r 1 at 304r
336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
register: %vreg1 +[336r,448B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0)
352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
register: %vreg1 replace range with [336r,352r:1) RESULT: [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0,...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...00_Reg128:%vreg3
> R600_Reg32:%vreg28
> register: %vreg3 replace range with [304r,320r:1) RESULT:
> [304r,320r:1)[320r,416r:0) 0 at 320r 1 at 304r
> 336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
> register: %vreg1 +[336r,448B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0)
> 352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1
> R600_TReg32:%vreg17
> register: %vreg1 replace range with [336r,352r:1) RESULT:
> [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
> 368B%vreg13<def> = MOV 1, 0, 0, 0...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Thank for your help. You're right, merging vreg32 and vreg48 is perfectly fine, sorry I missed that.
I "brute force" debuged by adding MachineFunction dump after each join, I think I found the issue : it's when vreg32 and vreg10 are merged.
vreg10 only appears in BB#3, and the join only occurs in BB#3 apparently even if vreg32 lives in the 4 machine blocks
After joining, there
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and