Displaying 8 results from an estimated 8 matches for "0bbb".
Did you mean:
0bb0
2005 Jan 17
0
chan_capi outgoing msn
Vincent Guidoux schrieb:
> Now i have a un new prob
>
> Executing Dial("SIP/2500-0bbb", "CAPI/@4202270:0796273153|30|r") in new
> stack
> Jan 17 13:14:39 NOTICE[4146]: chan_capi.c:1173 capi_request: didn't find
> capi device with outgoing msn = 4202270. you should check your config
well the error message says it all. 'you should check your config'...
2013 May 22
2
Creating nested hash from nested active record results
Hello,
I''m trying to find a very abstract and "one size fits all" for
converting nested active record results to nested hashes. It''s easy,
to do one level deep as such:
[code]
results_to_hash = Hash[ found_categories.map{ |c| [c.id, c.title]}]
[/code]
But, when I try to add another collection to the mix, it completely
borks and the results_to_hash only returns an
2009 Jan 12
1
Deliver *sometimes* delivers via /tmp?
...plete
SELinux messages. run sealert -l 19445c54-9537-45ec-8f3e-7718364b1f1f
Jan 6 16:44:29 jukebox setroubleshoot: SELinux is preventing the
deliver from using potentially mislabeled files
(./dovecot.deliver..1231256667.7940.53f0f908f5a97712). For complete
SELinux messages. run sealert -l 0cb74c68-0bbb-4de6-a15f-0bb5fdffcf90
Jan 6 16:44:29 jukebox setroubleshoot: SELinux is preventing the
deliver from using potentially mislabeled files
(2F746D702F646F7665636F742E64656C697665722E2E313233313235363636372E373934302E35336630663930386635613937373132202864656C6574656429).
For complete SELinux messages....
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...%vreg0
RETURN
# End machine code for function main.
# *** IR Dump Before Merge disjoint stack slots ***:
# Machine code for function main: SSA
Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
0BBB#0: derived from LLVM BB %0
Live Ins: %T1_W %T1_Z %T1_Y %T1_X
16B%vreg3<def> = COPY %T1_X; R600_TReg32:%vreg3
32B%vreg2<def> = COPY %T1_Y; R600_TReg32:%vreg2
48B%vreg1<def> = COPY %T1_Z; R600_TReg32:%vreg1
64B%vreg0<def> = COPY %T1_W; R600_TReg32:%vreg0
80B%vreg4<def&g...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...COPY %vreg10<kill>; R600_Reg128:%vreg48,%vreg10
register: %vreg48 phi-join +[1120r,1168B:2)
1136B%vreg49<def> = COPY %vreg11<kill>; R600_Reg32:%vreg49,%vreg11
register: %vreg49 phi-join +[1136r,1168B:2)
1152BJUMP <BB#1>, pred:%noreg
Computing live-in reg-units in ABI blocks.
0BBB#0 T1_X#0 T1_Y#0 T1_Z#0 T1_W#0
Created 4 new intervals.
********** INTERVALS **********
T1_W = [0B,16r:0)[848r,864r:1) 0 at 0B-phi 1 at 848r
T1_X = [0B,64r:0)[752r,864r:1) 0 at 0B-phi 1 at 752r
T1_Y = [0B,48r:0)[784r,864r:1) 0 at 0B-phi 1 at 784r
T1_Z = [0B,32r:0)[816r,864r:1) 0 at 0B-phi 1 at 8...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
..._Reg128:%vreg48,%vreg10
> register: %vreg48 phi-join +[1120r,1168B:2)
> 1136B%vreg49<def> = COPY %vreg11<kill>; R600_Reg32:%vreg49,%vreg11
> register: %vreg49 phi-join +[1136r,1168B:2)
> 1152BJUMP <BB#1>, pred:%noreg
> Computing live-in reg-units in ABI blocks.
> 0BBB#0 T1_X#0 T1_Y#0 T1_Z#0 T1_W#0
> Created 4 new intervals.
> ********** INTERVALS **********
> T1_W = [0B,16r:0)[848r,864r:1) 0 at 0B-phi 1 at 848r
> T1_X = [0B,64r:0)[752r,864r:1) 0 at 0B-phi 1 at 752r
> T1_Y = [0B,48r:0)[784r,864r:1) 0 at 0B-phi 1 at 784r
> T1_Z = [0B,32r:0)[81...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...function main.
>
> # *** IR Dump Before Merge disjoint stack slots ***:
> # Machine code for function main: SSA
> Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
> Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
>
> 0BBB#0: derived from LLVM BB %0
> Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> 16B%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> 32B%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> 48B%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
> 64B%vreg14<def> = COPY %T1_X; R600...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...CFG: BB#1
# End machine code for function main.
# *** IR Dump Before Merge disjoint stack slots ***:
# Machine code for function main: SSA
Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
0BBB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
16B%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
32B%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
48B%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
64B%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
80B%vreg18...